At present, semiconductor process technology is capable of creating features having dimensions well into the submicron range. At this level of miniaturization, feature size variations due to what is commonly referred to as the xe2x80x9coptical proximity effectxe2x80x9d can become significant. In general, proximity effects are variations in feature dimensions that are due to the proximity of other nearby features. In particular, optical proximity effects are proximity effects that occur during optical lithography. As a result of optical proximity effects, the size of a given feature can vary based on its spacing from other features.
Among the phenomena contributing to optical proximity effects are diffraction patterns associated with imaged features. One example of an optical proximity effect is the difference in dimension that can occur between an isolated printed line and a printed line in a dense array of equal lines.
Specific consequences of optical proximity effects include situations where internal features, which are surrounded by other features, and peripheral features, which are not, differ substantially. (Under these circumstances, optical proximity effects are frequently referred to as optical edge effects.) For example, at present, during photolithographic processes at submicron feature sizes, peripheral photoresist features frequently display a significant optical edge effect. As a result, etched silicon trenches, among other features, are frequently and adversely affected. Accordingly, devices employing etched silicon trenches, such as trench DMOSFETS (double diffused metal oxide semiconductor field effect transistors), trench Schottky barrier rectifiers, DRAM (dynamic random access memory) devices, and devices in which trenches are used to isolate separate integrated circuits, are likewise frequently and adversely effected by the optical edge effect.
An example of such an edge effect is presented in FIG 1A and 1B. These figures illustrate a situation where trenches are etched using apertures between the photoresist features. More specifically, as seen in FIG 1A, a silicon substrate 10 is provided with photoresist features 15a, 15b, 15c, 15d via an optical lithography process. As shown in this figure, the internal features 15a, 15b and 15c, each of which is positioned between other features (the feature to the left of internal feature 15a is not shown here), have substantially vertical sidewalls. Unfortunately, as a consequence of the optical edge effect discussed herein, peripheral feature 15d, which is not positioned between other features, has a substantially oblique sidewall as shown.
FIG. 1B illustrates the results that are obtained after subjecting the photoresist-patterned silicon substrate to an etch step. As can be seen in this figure, due to the substantially vertical nature of the sidewalls associated with photoresist features 15a, 15b and 15c, silicon sidewalls 10a, 10b and 10c are also substantially vertical. In contrast, due to the substantially oblique nature of the sidewalls associated with photoresist feature 15d, silicon sidewall 10d is also substantially oblique, resulting in a sharp corner at the trench bottom.
In other instances, a silicon substrate is etched using a silicon oxide or silicon nitride photomask. Referring to FIG. 2A, a silicon oxide or nitride layer is etched via photoresist features 15a, 15b, 15c, 15d, to form silicon oxide or silicon nitride features 17a, 17b, 17c, 17d on silicon substrate 10. As shown in this figure, the internal photoresist features 15a, 15b, 15c, each of which is positioned between other photoresist features, have substantially vertical sidewalls, while the peripheral photoresist feature 15d, which is not positioned between other photoresist features, has a substantially oblique sidewall. The same is true of the silicon oxide or nitride features 17a-17d. Photoresist features 15a, 15b, 15c and 15d are then removed, leaving only oxide or nitride features 17a, 17b, 17c and 17d. FIG. 2B illustrates the result of etching the silicon substrate 10 using silicon oxide or silicon nitride features 17a, 17b, 17c and 17d alone as masking features. As can be seen, the results are largely the same as those achieved when the substrate 10 is etched using photoresist features 15a, 15b, 15c and 15d (see FIG. 1B). Specifically, due to the substantially vertical nature of the sidewalls associated with silicon oxide or silicon nitride features 17a, 17b, 17c, silicon sidewalls 10a, 10b and 10c are also substantially vertical. Furthermore, silicon oxide or silicon nitride feature 17d has a substantially oblique sidewall, which results in a trench feature having a substantially oblique silicon sidewall 10d and an accompanying sharp corner at the trench bottom.
In still other instances, a silicon substrate is etched through a mask defined by both photoresist features and silicon oxide or nitride features. As shown in FIG. 3, the internal photoresist features 15a, 15b, 15c, each of which is positioned between other photoresist features, have substantially vertical sidewalls, while the peripheral photoresist feature 15d, which is not positioned between other photoresist features, has a substantially oblique sidewall as shown. The same is true of the silicon oxide or nitride features 17a-17d. As to the silicon substrate 10, due to the substantially vertical nature of the sidewalls associated with features 15a/17a, 15b/17b and 15c/17c, silicon sidewalls 10a, 10b and 10c are also substantially vertical. In contrast, due to fact that feature 15d/l7d is oblique and is comprised of a combination of photoresist and oxide or nitride, a sharp corner is formed at the trench bottom, as was observed in connection with FIGS. 1 and 2B. Moreover, the silicon substrate 10 is undercut at the interface that is formed with the oxide or nitride feature 17d. 
In each of the above cases, the optical proximity effect produces undesirable trench characteristics, including sloping sidewalls and sharp-cornered bottoms. Accordingly, there is a need in the art to address optical proximity effects on etched trench features.
Others have addressed problems arising from optical proximity effects in DRAM applications by putting dummy trenches around the cells. See, e.g., J. Fung Chen, Tom Laidig, Kurt E. Wampler and Roger Caldwell, xe2x80x9cPractical Method for Full-Chip Optical Proximity Correction,xe2x80x9d SPIE Proceedings, Vol.3051,1997; J. Fung Chen, Tom Laidig, Kurt E. Wampler and Roger Caldwell, xe2x80x9cAn OPC Roadmap to 0.14 mm Design Rules,xe2x80x9d paper presented at BACUS, 1997; J. Li, D. Bernard, J. Rey, V. Boksha, xe2x80x9cModel-Based Optical Proximity Correction Including Photo-resist Effects,xe2x80x9d Proc. SPIE, V.3051, 1997, P.643-651; N. Shamma, F. Sporon-Fiedler, E. Lin, xe2x80x9cA Method for Correction of Proximity Effect in Optical Lithography,xe2x80x9d KTI Microlithography Seminar Interface ""91, P.145; Chris A. Mack, xe2x80x9cEvaluating Proximity Effects Using 3-D Optical Lithography Simulation,xe2x80x9d Semiconductor International July 1996 P.237; O. Otto etc, xe2x80x9cAutomated optical proximity correctionxe2x80x94a rule-based approach,xe2x80x9d SPIE Proceedings, V.2197,P.278, 1994; A. Kornblit etc, xe2x80x9cRole of etch pattern fidelity in the printing of optical proximity corrected photomasks,xe2x80x9d EIPB""95, 1995.
However, a need nonetheless remains in the art for alternative methods of addressing these problems.
These and other needs in the art are addressed by the present invention.
According to a first aspect of the present invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate.
In one preferred embodiment, the at least one buffer layer is provided over the semiconductor substrate in the area of the at least one shallow peripheral trench, while no buffer layer is provided over the semiconductor substrate in the area of the plurality of internal trenches.
In another preferred embodiment, at least one buffer layer is provided over the semiconductor substrate in the area of the at least one shallow peripheral trench and at least one buffer layer is provided over the semiconductor substrate in the area of the plurality of internal trenches. However, the at least one buffer layer in the area of the plurality of internal trenches is thinner than the at least one buffer layer in the area of the at least one shallow peripheral trench. (For example, the at least one buffer layer in the area of the plurality of internal trenches can consist of a single buffer layer, while the at least one buffer layer in the area of the at least one shallow peripheral trench can consist of two buffer layers.) As a result, each internal trench extends through the at least one buffer layer in the area of the plurality of internal trenches and into the semiconductor substrate, while each shallow peripheral trench does not extend through the at least one buffer layer in the area of the at least one shallow peripheral trench (and thus does not extend into the semiconductor substrate).
According to another aspect of the present invention, a method of providing trenches in a semiconductor substrate is provided. The method comprises (1) providing a semiconductor substrate; (2) providing a patterned etch resistant layer over the substrate, the patterned layer having a plurality of trench apertures comprising (a) at least one peripheral trench aperture and (b) a plurality of internal trench apertures; (3) providing at least one buffer layer between each peripheral trench aperture and the semiconductor substrate; and (4) conducting an etching process, wherein an internal trench is etched in the semiconductor substrate at each internal trench aperture position, and a peripheral trench is prevented from being etched into the semiconductor substrate at each peripheral aperture position by the at least one buffer layer.
In one preferred embodiment, the method further comprises providing at least one buffer layer between each internal trench aperture and the semiconductor substrate. However, the at least one buffer layer between each peripheral trench aperture and the semiconductor substrate has an aggregate thickness that is greater than the at least one buffer layer between each internal trench aperture and the semiconductor substrate. (For example, the at least one buffer layer between each internal trench aperture and the semiconductor substrate can consist of a single buffer layer, while the at least one buffer layer between each peripheral trench aperture and the semiconductor substrate consists of two buffer layers.) As a result, an internal trench is etched through the at least one buffer layer and into the semiconductor substrate at each internal trench aperture position during the etching procedure, while a trench is not etched through the at least one buffer layer (and hence not into the substrate) at each peripheral trench aperture position.
Preferred buffer layers include oxide layers and nitride layers. A preferred substrate is a silicon substrate.
A number of devices can be used in connection with the modified substrate and method of the present invention, including trench DMOS transistors, trench Schottky barrier rectifiers, and a DRAM device.
According to a further aspect of the present invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided. The structure comprises: (1) a substrate of a first conductivity type; (2) a body region on the substrate having a second conductivity type, wherein the peripheral and internal trenches extend through the body region; (3) an insulating layer that lines each of the peripheral and internal trenches; (4) a first conductive electrode overlying each insulating layer; and (5) source regions of the first conductivity type in the body region adjacent to the each internal trench, but not adjacent to the at least one peripheral trench. The structure can also comprise a drain electrode disposed on a surface of the substrate opposing the body region and a source electrode disposed over at least a portion of the source regions.
Preferably, the first conductivity type is n-type conductivity and the second conductivity type is p-type conductivity. Preferably, the insulating layer is an oxide layer and the conductive electrode comprises polysilicon. In certain preferred embodiments, the trench DMOS transistor structure further comprises an insulating region (such as a borophosphosilicate glass structure) over each first conductive electrode in the internal trenches.
One advantage of the present invention is that adverse optical edge effects associated with peripheral trench features are dealt with in an effective and economical manner.
Another advantage of the present invention is that the performance of products with peripheral trench features, such as trench DMOS devices, trench Schottky battier rectifiers, DRAM devices, and other devices employing peripheral trench features, is substantially improved.
These and other embodiments and advantages of the present invention will become readily apparent upon review of the Detailed Description and Claims to follow.